The present invention relates to a page buffer of a non-volatile memory device with an improved structure and a programming method of the non-volatile memory device.
In recent years, there has been an increasing demand for non-volatile memory devices which can be programmed and erased electrically and do not need a refresh function of rewriting data at certain intervals. To enhance the level of integration of memory devices, more than one bit of data is stored in one cell.
The non-volatile memory device typically includes a memory cell array in which cells having data stored therein are arranged in matrix form, and a page buffer for writing memory into specific cells of the memory cell array and reading memory stored in specific cells. The page buffer includes a bit line pair connected to a specific memory cell, a register for temporarily storing data to be written into a memory cell array or temporarily storing data of a specific cell, which is read from a memory cell array, a sense node for sensing a voltage level of a specific bit line or register, and a bit line select unit for controlling whether the specific bit line is connected to the sense node.
In a typical page buffer structure, as the line width of a fabrication process decreases and the level of integration increases, capacitance between bit lines increases and a load on each bit line also increases. To solve these problems, there is a need to provide a non-volatile memory device that is able to reduce the load on the bit lines by improving the structure of the memory cell array and the page buffer.
The improved page buffer includes two registers, both of which are responsible for upper and lower memory cells, respectively. Thus, a multi-level cell program of a specific cell is performed using only one register. However, only one register can be vulnerable to the multi-level cell program. Accordingly, there is a need to provide a programming method enabling a multi-level cell program with only one register.